The present invention relates to a semiconductor memory device, and more particularly to improvements on a read out circuit in a nonvolatile memory device.
In a semiconductor memory device, bit lines contained in its read out circuit are accompanied inevitably by stray capacitance. The stray capacitance impedes the memory operation. A measure, which has been taken for this problem, employs a clamp circuit connected to each bit line. The clamp circuit clamps a bit signal to restrict the stray capacitance distributed in association with the bit line. For a short memory cycle, this measure effectively restricts the stray capacitance problem. For a long memory cycle, however, it ineffectively restricts the stray capacitance. When the memory operation cycle is long, weak inversion currents are produced in the transistors in the clamp circuit. The weak inversion currents increase a maximum amplitude of the bit signal. The increased maximum amplitude of the bit signal elongates a discharge time of the bit line, and therefore elongates an access time of the memory device.
A semiconductor memory device of prior art will be described referring to FIG. 1. The semiconductor memory device shown in FIG. 1 is an EPROM. Each memory cell of the memory device is a MOS (metal oxide semiconductor) transistor of the double silicon structure with a floating gate. In FIG. 1, reference numeral 12 designates a word line, and reference numeral 13 designates a bit line. A bit select transistor 14 is inserted in the bit line 13. A relatively large capacitance is distributed over the bit line. The capacitance delays a signal propagating on the bit line 13. To minimize the signal delay, a clamp circuit 19 consisting of transistors 15 and 16 is provided and clamps the amplitude of the signal on the bit line 13 to a small limited value. The amplitude limited signal is applied to a resistive load 17. The signal appearing across the load 17 is amplified by a post stage amplifier (not shown).
A delay time of the signal on the bit line 13 is expressed by C.sub.BIT .times..DELTA.V/I.sub.CELL where C.sub.BIT is the capacitance of the bit line 13, .DELTA.V an amplitude of a signal on the bit line 13, and I.sub.CELL a cell current flowing through the transistor 11. The expression shows that a delay time of the signal on the bit line 13 is proportional to the signal amplitude on the bit line 13. The amplitude of the bit line signal is set at approximately 0.2 V.
The clamp circuit 19 clamps a maximum signal voltage of the bit line signal to 1 V=V.sub.B -V.sub.TN, specifying that the output voltage V.sub.B of a bias circuit 18 is 2 V, the power source potential V.sub.DD is 5 V, and the threshold voltage V.sub.TN of each transistor 15 and 16 is 1 V.
However, only when the memory device operates in an ordinary short operating cycle, the maximum potential on the bit line 13 can be limited to 1 V. In a long operating cycle, weak inversion currents flow through the transistors 15 and 16 of the clamp circuit, so that the maximum potential on the bit line exceeds 1 V. As a result, the signal amplitude .DELTA.V is increased up to about 0.5 V, for example. Accordingly, a discharge time of the bit line is longer than that in the case of 0.2 V for the maximum potential. Therefore, an access time to the memory is also long.